block diagram 0 1 clk0 /clk0 clk_sel q 0 /q 0 q 1 /q 1 q 2 /q 2 q 3 /q 3 q 4 /q 4 q 5 /q 5 q 6 /q 6 q 7 /q 7 q 8 /q 8 q 9 /q 9 v bb v cc v ee clk1 /clk1 v cc v ee v ee v ee v ee 75k ? 75k ? 75k ? 75k ? 75k ? 75k ? 75k ? features 2.5v and 3.3v power supply options guaranteed ac parameters over temperature: ? max = 3ghz < 25ps output-to-output skew < 320ps t r /t f < 475ps propagation delay wide temperature range: ?0 c to +85 c differential design v bb output for single-ended input applications fully compatible with industry standard 100k i/o levels available in 32-pin tqfp package the SY100EP111U is a high-speed, low skew 1-to-10 differential fanout buffer designed for clock distribution in new, high-performance systems. the internal 2:1 mux allows the input to select between two differential clock sources. the device is specifically designed for low skew. the interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot. the v bb output is intended for use as a reference voltage for single-ended reception of ecl signals to that device only. when using v bb for this purpose, it is recommended that v bb is decoupled to v cc via a 0.01 f capacitor. 2.5v/3.3v 1:10 differential lvpecl/lvecl/hstl clock driver description SY100EP111U final 1 rev.: a amendment: /3 issue date: september 2001 pin configuration 32 31 30 29 28 27 26 25 9 10111213141516 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 vcc clk_sel clk0 /clk0 vbb clk1 /clk1 vee q3 /q3 q4 /q4 q5 /q5 q6 /q6 vcc q0 /q0 q1 /q1 q2 /q2 vcc vcc /q9 q9 /q8 q8 /q7 top view tqfp t32-1 q7 vcc
2 SY100EP111U micrel pin function clk0, /clk0 lvpecl, lvecl, hstl clock inputs: clk0 input includes a 75k ? pull-down. default is low if left floating. /clk0 includes an internal 75k ? pull-up and pull-down. default state is v cc /2. clk1, /clk1 lvpecl, lvecl, hstl clock inputs: clk input includes a 75k ? pull-down. default is low if left floating. /clk includes an internal 75k ? pull-up and pull-down. default state is v cc /2. q0 to q9 lvpecl/lvecl outputs. /q0 to /q9 complementary lvpecl/lvecl outputs. clk_sel lvpecl/lvecl clock select input: internal 75k ? resistor connected to v ee . when left floating, the default condition is low. v bb reference voltage: ac coupled or single- ended input applications. v cc positive power supply: bypass with 0.1 f// 0.01 f low esr capacitors. v ee negative power supply: lvpecl operation, connect to gnd. pin names clk_sel active input 0 clk0, /clk0 1 clk1, /clk1 function table symbol rating value unit v cc ? ee power supply voltage 6.0 v v in input voltage (v cc = 0v, v in not more negative than v ee ) ?.0 to 0 v input voltage (v ee = 0v, v in not more positive than v cc ) +6.0 to 0 i out output current ?ontinuous 50 ma ?urge 100 i bb v bb sink/source current (2) 0.5 ma t a operating temperature range ?0 to +85 c t store storage temperature range ?5 to +150 c ja package thermal resistance ?till-air 50 c/w (junction-to-ambient) ?00lfpm 42 jc package thermal resistance 20 c/w (junction-to-case) absolute maximum ratings (1) notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum r atlng conditions for extended periods may affect device reliability. 2. due to the limited drive capability, use for inputs of same package only.
3 SY100EP111U micrel t a = 40 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v cc power supply voltage (lvpecl) 2.375 3.8 2.375 3.8 2.375 3.8 v (lvecl) ?.8 ?.375 ?.8 ?.375 ?.8 ?.375 v i ee power supply current 55 120 70 120 85 120 ma i ih input high current 150 150 150 av in =v ih i il input low current clk0, clk1 0.5 0.5 0.5 av in =v il /clk0, /clk1 ?50 ?50 ?50 av in =v il c in input capacitance 2 pf dc electrical characteristics (1) notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. t a = 40 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v ih input high voltage 2135 2420 2135 2420 2135 2420 mv (single-ended) v il input low voltage 1355 1675 1355 1675 1355 1675 mv (single-ended) v ol output low voltage 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv 50 ? to v cc ?v v oh output high voltage 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv 50 ? to v cc ?v v bb reference voltage (2) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage 1.2 v cc 1.2 v cc 1.2 v cc v common mode range (3) lvpecl dc electrical characteristics (1) v cc = 3.3v 10%; v ee = 0v notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. input and output v aries 1:1 with v cc . 2. single-ended input operation is limited v cc 3.0v in lvpecl mode. v bb reference varies 1:1 with v cc . 3. v ihcmr (min) varies 1:1 with v ee , v ihcmr (max) varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal.
4 SY100EP111U micrel t a = 40 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v ih input high voltage 1335 1620 1335 1620 1335 1620 mv (single-ended) v il input low voltage 555 875 555 875 555 875 mv (single-ended) v ol output low voltage 555 680 805 555 680 805 555 680 805 mv 50 ? to v cc ?v v oh output high voltage 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv 50 ? to v cc ?v v ihcmr input high voltage 1.2 v cc 1.2 v cc 1.2 v cc v common mode range (2) lvpecl dc electrical characteristics (1) v cc = 2.5v 5%, v ee = 0v notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. input and output v aries 1:1 with v cc . 2. v ihcmr (min) varies 1:1 with v ee , v ihcmr (max) varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. t a = 40 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit v ih input high voltage 1200 1200 1200 mv v il input low voltage 400 400 400 mv v x input crossover voltage 680 900 680 900 680 900 mv hstl dc electrical characteristics v cc = 2.375v to 3.8v; v ee = 0v t a = 40 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage ?945 ?625 ?945 ?625 ?945 ?625 mv (single-ended) v ih input high voltage ?165 ?880 ?165 ?880 ?165 ?880 mv (single-ended) v ol output low voltage ?945 ?820 ?695 ?945 ?820 ?695 ?945 ?820 ?695 mv 50 ? to v cc ?v v oh output high voltage ?145 ?020 ?895 ?145 ?020 ?895 ?145 ?020 ?895 mv 50 ? to v cc ?v v bb output reference voltage (2) ?525 ?425 ?325 ?525 ?425 ?325 ?525 ?425 ?325 mv v ihcmr input high voltage v common mode range (3) v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 lvecl dc electrical characteristics (1) v ee = ?.375v to ?.8v; v cc = 0v notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. 2. single-ended input operation is limited v ee ?.0v in lvecl mode. 3. v ihcmr (min) varies 1:1 with v ee . the v ihcmr range is referenced to the most positive side of the differential input signal.
5 SY100EP111U micrel product ordering code ordering package operating package code type range marking SY100EP111Uti t32-1 industrial xep111u SY100EP111Utitr* t32-1 industrial xep111u t a = 40 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition f max maximum frequency (1) 3 ? 3 ghz t plh propagation delay (diff.) 325 400 475 325 400 475 325 400 475 ps t phl t skew within-device skew 20 25 20 25 20 25 ps (2) part-to-part skew 85 150 85 150 85 150 ps (3) t jitter cycle-to-cycle jitter (rms) 0.2 < 1 0.2 < 1 0.2 < 1 ps v pp minimum input swing (4) 150 800 1200 150 800 1200 150 800 1200 mv t r , t f output rise/fall time 105 180 255 105 200 275 105 230 320 ps (20% to 80%) ac electrical characteristics (lvpecl) v cc = 2.375 to 3.8v, v ee = 0v; (lvecl) v ee = ?.375v to ?.8v, v cc = 0v notes: 1. measured with 750mv clock signal, 50% duty cycle. all loading with a 50 ? to v cc ?.0v. 2. input clock to any output (q0 to q9); differential. 3. measured for same transitions. 4. see ?iming waveform. timing waveform clk(0:1) /clk(0:1) 150mv to 1200mv *tape and reel
6 SY100EP111U micrel typical characteristics 200 300 400 500 600 700 800 900 0 500 1000 1500 2000 2500 3000 3500 4000 output amplitude (mvp-p) frequency (mhz) frequency response vs. output amplitude v sup = 2.5v v diffin = 800mv frequency response vs. output amplitude @2.5v 200 300 400 500 600 700 800 900 0 500 1000 1500 2000 2500 3000 3500 4000 output amplitude (mvp-p) frequency (mhz) frequency response vs. output amplitude v sup = 3.3v v diffin = 800mv frequency response vs. output amplitude @3.3v
7 SY100EP111U micrel termination recommendations r2 82 ? r2 82 ? z o = 50 ? z o = 50 ? +3.3v +3.3v v t = v cc 2v r1 130 ? r1 130 ? +3.3v figure 1. parallel termination thevenin equivalent notes: 1. for +2.5v systems: r1 = 250 ? r2 = 62.5 ? z = 50 ? z = 50 ? 50 ? 50 ? 46 ? to 50 ? +3.3v +3.3v source destination r b figure 2. three-resistor y termination notes: 1. power-saving alternative to thevenin termination. 2. place termination resistors as close to destination inputs as possible. 3. r b resistor sets the dc bias voltage, equal to v t . +3.3v +3.3v 50 ? z o = 50 ? 0.01 f v bb r2 82 ? +3.3v +3.3v r1 130 ? r1 130 ? r2 82 ? v t = v cc 2v q /q +3.3v figure 3. terminating unused i/o notes: 1. unused output (/q) must be terminated to balance the output. 2. micrel's differential i/o logic devices include a v bb reference pin . 3. connect unused input through 50 ? to v bb . bypass with a 0.01 f capacitor to v cc , not gnd. 4. for +2.5v systems: r1 = 250 ? , r2 = 62.5 ? .
8 SY100EP111U micrel micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2001 micrel incorporated 32 lead thin quad flatpack (t32-1) rev. 01
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